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DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register
August 1986 Revised March 2000
DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register
General Description
These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching transients to simplify system design. The load mode is established by the shift/load input. When HIGH, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When LOW, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the LOW-to-HIGH level edge of the clock pulse through a two-input NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking; holding either LOW enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
Ordering Code:
Order Number DM74LS166M DM74LS166WM DM74LS166N Package Number M16A M16B N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
(c) 2000 Fairchild Semiconductor Corporation
DS006400
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DM74LS166
Function Table
Inputs Clear Shift/ Load L H H H H H X X L H H X Clock Inhibit X L L L L H X L X X X H L X Clock Serial Parallel A...H X X a...h X X X Internal Outputs QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 L QH0 h QGn QGn QH0 Output QH
H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, Q B, QH, respectively, before the indicated steady-state input conditions were established QAn, QGn, = The level of QA, QG, respectively, before the most recent transition of the clock
Logic Diagram
Timing Diagram
Typical Clear, Shift, Load, Inhibit and Shift Sequences
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DM74LS166
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 4) Setup Time (Note 4) Hold Time (Note 4) Free Air Operating Temperature Clock Clear Mode Data 0 0 20 20 30 20 0 0 70 Parameter Min 4.75 2 0.8 -0.4 8 25 20 Nom 5 Max 5.25 Units V V V mA mA MHz MHz ns ns ns C
Note 2: CL = 15 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 4: TA = 25C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 6) VCC = Max (Note 7) -20 22 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 -0.4 -100 38 mA A mA mA mA Min Typ (Note 5) Max -1.5 Units V V
V
Note 5: All typicals are at VCC = 5V, TA = 25C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: With all outputs OPEN, 4.5V applied to the serial input, all other inputs except the CLOCK grounded, ICC is measured after a momentary ground, then 4.5V is applied to the CLOCK.
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DM74LS166
Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min fMAX tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output Clock to Output Clock to Output Clear to Output 25 8 8 6 35 35 30 Max RL = 2 k CL = 50 pF Min 20 38 41 36 Max MHz ns ns ns Units
Parameter Measurement Information
Voltage Waveforms
Test Table for Synchronous Inputs
Data Input for Test H Serial Input 0V 4.5V Shift/Load Output Tested (See Note C) QH at TN+1 QH at TN+8
Note A: The clock pulse has the following characteristics: tW(clock) 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics: tW(clear) 20 ns and tHOLD = 0 ns. When testing fMAX, vary the clock PRR. Note B: A clear pulse is applied prior to each test. Note C: Propagation delay times (tPLHand tPHL) are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test. Note D: tn = bit time before clocking transition tn+1 = bit time after one clocking transition tn+8 = bit time after eight clocking transitions Note E: VREF = 1.3V.
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DM74LS166
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B
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DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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